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394 Chapter 15
W-CDMA Uplink Digital Modulation for Receiver Test
Setting Up a Multiple PRACH Signal
access slot.
In order to clearly show the second UE1 PRACH transmission on the PSA, we will
select an access slot that will not be occupied by other UEs that are configured later in
this task.
c. Press
15 > Enter.
2. Configure UE2 for a single PRACH transmission starting in access slot 2.
a. Highlight the first access slot position for UE2.
b. Press
2 > Enter.
This PRACH will start its transmission between the first preamble for UE1 and its
message part. The message part for UE2 will begin during the first message part for UE1.
For the length of time that the message part for UE1 and UE2 occupy the same access
slots, they will be additive creating a stronger signal during that time period.
3. Leave UE4 to transmit a single PRACH starting in access slot 0.
This PRACH will occupy the same access slots as the first PRACH transmission for UE1.
UE1 and UE4 will be additive during this transmission time period creating a higher
signal level for the same period of time.
4. Press
Apply Channel Setup.
When the Apply Needed annunciator appears, press the
Apply Channel Setup softkey. You
will not see a change in the signal until you press this softkey.
Figure 15-32 shows both the completed timing setup display and a graphical representation of
the setup by access slot when this procedure was used to configure the multiple PRACH
signal. Figure 15-33 on page 397 shows the output of the ESG, with the same configuration,
on the Agilent E4440A PSA Spectrum Analyzer.
- User’s Guide 1
- Contents 10
- 1 Signal Generator Overview 17
- Signal Generator Features 18
- Front Panel Overview 23
- ΦM. For all these 24
- 10. EXT 2 INPUT 25
- 11. Help Key 25
- 12. Trigger Key 25
- 13. LF OUTPUT 26
- 14. RF OUTPUT 26
- 15. Mod On/Off Key 26
- 16. RF On/Off Key 26
- 17. Numeric Keypad 26
- 31. DATA (Input Connector) 29
- 32. Q (Input Connector) 29
- 33. I (Input Connector) 29
- Front Panel Display 30
- 2. Annunciators 31
- Utility > Error Info 33
- Rear Panel Overview 34
- 5. I-bar OUT Connector 36
- 6. I OUT Connector 36
- 8. Q OUT Connector 37
- 9. Q-bar OUT Connector 38
- 10. EVENT 1 Connector 38
- 11. EVENT 2 Connector 39
- 12. PATT TRIG IN Connector 39
- 13. AUX I/O Connector 40
- 14. DIG I/Q I/O Connector 41
- 15. AC Power Receptacle 42
- 16. GPIB Connector 42
- 17. RS 232 Connector 42
- 18. LAN Connector 43
- 19. TRIG OUT Connector 43
- 20. BURST GATE IN Connector 43
- 21. TRIG IN Connector 44
- 22. 10 MHz IN Connector 44
- 23. SWEEP OUT Connector 44
- 24. 10 MHz OUT Connector 44
- 30 Chapter 1 46
- Signal Generator Overview 46
- Table 1-9 46
- Chapter 1 31 47
- 32 Chapter 1 48
- 2 Basic Operation 49
- Using Table Editors 50
- Table Editor Softkeys 51
- −20 dBm) 54
- Configuring a Swept RF Output 55
- −20 dBm to 0 dBm 56
- −2.5 > dBm 59
- First AM Menu 60
- Modulation Format is Off 60
- Modulation format is On 61
- Modulating the Carrier Signal 62
- Load/Store 67
- Store to File 67
- GPIB Listener Mode 69
- Using Data Storage Functions 70
- Recall or Save hardkey 74
- Delete All Sequences 74
- Enabling Options 75
- Enter terminator softkey 76
- 3 Basic Digital Operation 77
- Not all ARB formats 79
- Save Setup To Header softkey 80
- Dual ARB 83
- Player Softkey 83
- It does not Appear 83
- Select Waveform softkey 86
- ARB Off On to On 86
- Catalog Type softkey 88
- NVWFM softkey 89
- Storing a Header File 90
- Using the Dual ARB Player 92
- Creating Waveform Segments 93
- Playing a Waveform 96
- Editing Waveform Sequences 97
- ARB Player 100
- Save hardkey function with 101
- ARB Sample Clock 102
- Waveform Markers 103
- First-Level Softkey 104
- Not all ARB formats will 104
- Using Waveform Markers 106
- Setting the Marker Polarity 110
- Amplitude 110
- Verifying Marker Operation 114
- Using Waveform Triggers 115
- Amplitude > -10 > dBm 116
- RF On/Off hardkey to On 116
- Trigger hardkey 116
- Using External Triggering 117
- Generating the Waveform 118
- Configuring the RF Output 118
- How Power Peaks Develop 119
- Chapter 3 105 121
- Basic Digital Operation 121
- 108 Chapter 3 124
- FIR Filtering Options 125
- Using Waveform Clipping 127
- Understanding Burst Shape 129
- Burst Shape 132
- .4 > Enter 133
- .6 > Enter 133
- Editing Keys > Clear Text 134
- Edit Item 136
- −0.000076 8 −0.035667 137
- −0.001747 9 −0.116753 137
- −0.005144 10 −0.157348 137
- −0.004424 11 −0.088484 137
- Display Impulse Response 139
- Modifying the Coefficients 142
- Storing the Filter to Memory 143
- Differential Encoding 144
- Differential Data Encoding 145
- Using Differential Encoding 148
- −1.000000). These 4 149
- −1. The symbol rotates 150
- User-Defined I/Q Maps 152
- 0000 0.500000 1.000000 153
- 0001 −0.500000 1.000000 153
- 0010 0.500000 −1.000000 153
- 0011 −0.500000 −1.000000 153
- Moving I/Q Symbols 154
- User-Defined FSK Modulation 156
- Storing an FSK Modulation 157
- −600 > Hz 158
- −1.8 > kHz 158
- Creating and Using Bit Files 159
- Enter These Bit Values 161
- Hexadecimal Data 161
- Positi on 161
- Indicator 161
- Recalling a User File 162
- Cursor moves to new position 163
- Position indicator changes 163
- Bits 4C through 4F inverted 163
- Hex Data changed 163
- Apply Bit Errors 164
- Bit Errors > 5 > Enter 164
- 4 Analog Modulation 165
- Analog Modulation Waveforms 166
- Configuring AM 167
- Configuring FM 168
- Configuring ΦM 169
- Configuring Pulse Modulation 170
- Configuring the LF Output 171
- 158 Chapter 4 174
- Analog Modulation 174
- 5 AWGN Waveform Generator 175
- 6 BERT Testing 177
- Required Equipment 178
- Connecting the Test Equipment 179
- Selecting the BERT Trigger 181
- Starting BERT measurements 181
- Synchronizing to the TCH 189
- Mode > EDGE w/GSM 196
- Makers 196
- Adjusting the Delay Value 197
- Xsymbols()D 227.8–()3.693⁄= 197
- Block Diagram 200
- Clock Gate Function 201
- Clock/Gate Delay Function 202
- Clock Delay Function 203
- Triggering 205
- Data Processing 208
- Repeat Measurements 209
- Testing Signal Definitions 210
- RF Loopback BER–Option 300 211
- Erased Frame Detection 212
- Downlink Errors 212
- Frame Structure 212
- 198 Chapter 6 214
- BERT Testing 214
- 7 Bluetooth Signals 215
- Setting Up Packet Parameters 217
- Setting up Impairments 219
- AWGN Off On to On 220
- Using Burst 221
- Using Clock/Gate Delay 222
- Turning On a Bluetooth Signal 223
- 208 Chapter 7 224
- Bluetooth Signals 224
- 8 CDMA Digital Modulation 225
- −10 dBm 226
- −12.72) in table row 3 228
- Edit Channel Setup 229
- Edit Item > 4800 232
- Edit Item > −10 > dB 232
- Return 232
- Return > Return 233
- Preset 236
- Edit Item > –825 > kHz 237
- Edit Item > –10 > dB 237
- RF On/Off 238
- Editing Channel Setups 240
- Adjusting Code Domain Power 242
- Managing Noise 243
- Editing the Mobile Setup 246
- Scale to 0 dB 249
- Waveform 252
- IS-95A Modulation 254
- ” on page 242 257
- Edit Item > −625 > kHz 258
- Return > CDMA Off On 258
- 244 Chapter 8 260
- CDMA Digital Modulation 260
- 9 Custom Digital Modulation 261
- −5 dBm 262
- Edit Keys > Clear Text 264
- ” on page 249 265
- −10 dBm 266
- Modulation State 267
- 10 GPS Modulation 271
- Option Overview 272
- GPS Concepts 273
- Chip Clock Reference 275
- User Files 277
- GPS Operation 278
- −0.5 to 5.5 V 279
- GPS Ref (f0) softkey 280
- Testing Receiver Sensitivity 281
- Selecting the Data Format 284
- Setting Up the GPS Receiver 284
- 270 Chapter 10 286
- GPS Modulation 286
- Multitone Waveform Generator 287
- Removing a Tone 289
- Storing a Multitone Waveform 290
- Mode > Multitone 291
- 276 Chapter 11 292
- 12 Real Time TDMA Formats 293
- EDGE Framed Modulation 294
- GSM Framed Modulation 296
- DECT Framed Modulation 298
- PHS Framed Modulation 300
- PDC Framed Modulation 302
- NADC Framed Modulation 304
- TETRA Framed Modulation 306
- 292 Chapter 12 308
- Real Time TDMA Formats 308
- Component Test 309
- Edit Item > 2 > dB 312
- Edit Item > 3 > dB 312
- Edit Item > 1 > dB 312
- Edit Item > 8 313
- Edit Item > PN9 313
- Edit Item > 1 > Enter 313
- Composite 318
- Waveform Clip softkey 318
- Apply Multicarrier softkey 319
- W-CDMA Uplink Modulation 322
- Apply To Waveform softkey 325
- W-CDMA Concepts 327
- 312 Chapter 13 328
- Understanding TPC Values 329
- −4.02 dB, −3.02 dB 331
- −5.02 dB respectively 331
- field 332
- field has a range of 333
- field entry and the 333
- W-CDMA Frame Structures 336
- 322 Chapter 13 338
- 324 Chapter 13 340
- Table 13-3 DPDCH Fields 340
- Chapter 13 325 341
- Table 13-4 DPCCH Fields 341
- 326 Chapter 13 342
- 14 W-CDMA Downlink Digital 343
- Using W-CDMA Downlink 344
- Applying New Settings 350
- W-CDMA Downlink Concepts 352
- Transport 354
- Scramble Codes 355
- AWGN 3.84 MHz Values 357
- Flat Noise Bandwidth 357
- AWGN 7.68 MHz Entries 357
- Ec/No Channel Selection 358
- Chapter 14 345 361
- Equipment Setup 364
- Chapter 15 349 365
- Understanding the PRACH 366
- Preamble 367
- Message Part 368
- Power Control 370
- PRACH Power Setup softkey 371
- Power Control Modes 376
- − 10 Log[1 + 10 377
- 362 Chapter 15 378
- −20 > dBm 381
- 7 > dB 382
- 4 > Enter 382
- Edit Item > AICH 387
- 1 > Enter 387
- Multiple PRACH Overview 391
- Multiple PRACH 394
- ESG Carrier Power 395
- 506 > Enter 399
- Waiting for 400
- Trigger Received 400
- Softkey is now Active 400
- 10 ms TTI 402
- −25 dBm (preamble 405
- −30 dBm + 5 dB Pp-m) 405
- 15 > Enter 406
- 5 > Enter 406
- Clear All Pos of Selected UE 409
- 2 > Enter 410
- Apply Channel Setup 410
- Timing Settings 411
- Rear Panel Setup 416
- Configuring the ESGs 417
- Out of Sync 418
- Annunciator 418
- LF Out Off On to On 420
- Mode > W-CDMA 422
- Measure > Occupied BW 422
- 125 > Enter 424
- 10 > Enter 424
- TrCH State Off On to On 425
- TrCH Setup 425
- Edit Item > 1/3 Conv 426
- 256 > Enter 426
- Apply Channel Setup softkey 426
- 8 > Enter 428
- 416 Chapter 15 432
- Adding Noise 433
- 10 > dB 434
- −35 dB to −34 dB) 437
- Power Hold Off On to Off 438
- Power Hold Off On to On 438
- Reset to Initial Power 438
- Configuring the UE Setup 439
- Selecting an Output Signal 442
- Deselecting an Output Signal 443
- NONE(RPSO) 444
- Setting Equal Channel Powers 446
- W-CDMA Uplink Concepts 447
- Measure Setup 448
- Sync Source 455
- FClk SFN 455
- Synchronization Diagrams 460
- , and timeslot offset 461
- Synchronization Annunciator 467
- DPCH 3.84 MHz Values 471
- PRACH 3.84 MHz Values 471
- Eb/No Data Sources 472
- Data Source Field 472
- Chapter 15 457 473
- DPCCH/DPDCH Frame Structure 474
- Chapter 15 459 475
- Table 15-12 DPCCH Fields 475
- Table 15-11 DPDCH Fields 475
- 460 Chapter 15 476
- 16 Troubleshooting 477
- If You Encounter a Problem 478
- Cannot Turn Off Help Mode 479
- No RF Output 479
- SIGNAL GENERATOR 480
- OUTPUT CONTROL 480
- RF Output Power too Low 483
- Sweep Appears to be Stalled 484
- Cannot Turn Off Sweep Mode 484
- Data Storage 485
- Recall > 99 > Enter 486
- Signal Generator Lock-Up 487
- ΦM calibration 488
- Upgrading Firmware 489
- Chapter 16 475 491
- Troubleshooting 491
- 476 Chapter 16 492
- Numerics 493
- Index478 494
- Index 479 495
- Index480 496
- Index 481 497
- Index482 498
- Index 483 499
- Index484 500
- Index 485 501
- Index486 502
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