Agilent Technologies ESG Betriebsanweisung Seite 204

  • Herunterladen
  • Zu meinen Handbüchern hinzufügen
  • Drucken
  • Seite
    / 502
  • Inhaltsverzeichnis
  • FEHLERBEHEBUNG
  • LESEZEICHEN
  • Bewertet. / 5. Basierend auf Kundenbewertungen
Seitenansicht 203
188 Chapter 6
BERT Testing
Bit Error Rate Tester–Option UN7
Gate Delay Function in the Clock Mode
To use this function, the clock must be set to continuous mode.
In this example, the clock is used to delay the gate function. The clock of the internal error
detector was gated by the gate signal which is delayed by two clocks. Figure 6-23 shows that
CH0 and CH1 are the input of the clock and data from the rear panel input connectors of
UN7. CH2 is the gated clock through the AUX I/O connector.
Figure 6-23
CH0: BER CLK IN (rear panel SMB connector)
CH1: BER GATE IN (rear panel SMB connector)
CH2: BER TEST OUT (pin 20 of AUX I/O connector)
CH1
CH2
CH0
Seitenansicht 203
1 2 ... 199 200 201 202 203 204 205 206 207 208 209 ... 501 502

Kommentare zu diesen Handbüchern

Keine Kommentare