Agilent Technologies ESG Betriebsanweisung Seite 202

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186 Chapter 6
BERT Testing
Bit Error Rate Tester–Option UN7
Clock/Gate Delay Function
This function enables you to restore the timing relationship between the clock/gate timing as
it passes through the unit under test (UUT) and the packet data.
The shifted clock signal is emitted from pin 20 of the AUX I/O rear panel connector. When you
use the clock delay function, the clock signal to the BER CLK IN connector is delayed by the
clock delay function. When you use the gate delay function with the clock gate function, the
clock signal is gated by the gate signal which is delayed by the gate delay function.
To see the signal flow using the clock and gate functions, refer to Figure 6-20.
Figure 6-20
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