Agilent Technologies ESG Betriebsanweisung Seite 203

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Chapter 6 187
BERT Testing
Bit Error Rate Tester–Option UN7
Clock Delay Function
In this example, the clock delay function is off. Figure 6-21 shows the input of the internal
error detector of UN7 through AUX I/O and indicates that the data is delayed from the clock.
Figure 6-21
CH1: BER TEST OUT (pin 20 of AUX I/O connector)
CH2: BER MEAS END (pin 1 of AUX I/O connector)
In this example, the clock delay function is on. The rising edge of the clock was delayed by
200 ns and was adjusted to the center of the data. Figure 6-22 indicates the result of the using
the clock delay function.
Figure 6-22
CH1
CH2
CH1
CH2
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