Agilent Technologies N4970A Bedienungsanleitung PDF herunterladen (Seite 14)

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Agilent J-BERT M8020A High-Performance BERT

www.agilent.com/find/m8020a

• Data rates up to 8.5/ 16 Gb/s for pattern generator and error

detector. Extension to 32 Gb/s possible with M8061A multiplexer

• 1 to 4 16 Gb/s BERT channels in a 5-slot AXIe chassis

• Integrated and calibrated jitter injections: RJ, PJ1, PJ2, SJ, BUJ,

clk/2, SSC, sinusoidal interference

• 8- tap de-emphasis (positive and negative) up to 20 dB

• Interactive link training for PCI Express

• Built-in clock data recovery and equalization

• In situ calibration

• Modules and options are upgradeable

The high-performance Agilent J-BERT M8020A enables

fast, accurate receiver characterization of single- and

multi-lane devices running up to 16 or 32 Gb/s.

With today’s highest level of integration, the M8020A streamlines

your test setup. In addition, automated in situ calibration of signal

conditions ensures accurate and repeatable measurements. And, through

interactive link training, it can behave like your DUT’s link partner. All

in all, the J-BERT M8020A will accelerate insight into your design.

Target applications

R&D and test engineers who characterize, verify compliance of chips,

devices, boards and systems with serial I/O ports up to 16 Gb/s

and 32 Gb/s. The M8020A can be used to test popular serial bus

standards, such as: PCI Express®, USB, MIPI M-PHY, SATA/SAS,

DisplayPort, SD UHS-II, Fibre Channel, front-side and memory buses,

backplanes, repeaters, active optical cables, Thunderbolt, 10 GbE,

100GbE (optical and electrical), SFP+, CFP2/4 transceivers, CEI.

Specifications

For operating range 32 Gb/s: see M8061A

For operation up to 16 Gb/s:

J-BERT M8020A high-performance BERT with 4 channels

Pattern generator

• Operating range: 150 MHz to 8.5 GHz (option G08 or C08), 150 MHz

to 16.2 GHz (option G16 or C16). For extension to 32.4 Gb/s: use

M8061A in addition.

• Data outputs: 1 or 4 for 16 Gb/s (option 0G2 for second channel per

M8041/51A module)

• Output amplitude: 50 mV to 1.2 Vpp (single ended)

• Transition time: 15 to 20 ps typical (20-80%)

• De-emphasis: 8 taps positive/ negative (option 0G4)

• Intrinsic jitter: 8 ps pp typical

• Connectors: 3.5 mm (f)

• Supplementary outputs: trigger out, clock out

Pattern

• PRBS: 2

-1, n = 7,10, 11 15, 23, 23p, 31

•

Memory: 4 Gbit per channel

• Sequencer: 3 counted loop levels, 1 infinite loop

• Interactive link training for PCIe

Jitter tolerance test

• Calibrated jitter sources: multi-UI low-frequency jitter up to 5 MHz,

high-frequency jitter up to 1 UI @ 500 MHz (RJ, PJ1,PJ2, BUJ, sRJ),

clk/2 ±20 ps

• SSC:±5000ppm

• ISI:eightISItraces(seeM8048A)

• Interference:built-incommon-modeupto400mVanddifferential-

mode up to 30% of output amplitude

• Automatedjittertolerancetest

Analyzer

• Datainputs;1to4(option0A2forsecondchannelperM8041/51A

module)

• Clockrecovery:builtin,adjustableloopbandwidthupto20MHz

• Sensitivity:50mV

• CTLE:yes

• Connectors:3.5mm(f)

Ordering

J-BERT in 5 –slot AXIe chassis w/ emb. controller M8020A-BU1

J-BERT in 5 –slot AXIe chassis M8020A BU2

16 Gb/s BERT 2 ch with clock, 3-slot AXIe module M8041A

16 Gb/s BERT 2 ch, 2-slot AXIe module M8051A

32 Gb/s Multiplexer 2:1 with de-emphasis M8061A

System software for M8000 Series M8070A

* available options for M8041A:

8.5/16Gb/s, generator-only, 2nd channel generator/analyzer,

de-emphasis, jitter sources, interference sources, reference

clock multiplier, SER/FER analysis, link training, CTLE

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 39 40

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