Agilent Technologies J-BERT N4903B Bedienungsanleitung PDF herunterladen (Seite 6)

Calibrated and integrated jitter injection

• Periodic jitter, single and dual-tone (Option J10)

• Sinusoidal jitter (Option J10)

• Random jitter and spectrally distributed RJ (Option J10)

• Bounded uncorrelated jitter (Option J10)

• Intersymbol interference (ISI) (Option J20)

• Sinusoidal interference (Option J20)

• Spread spectrum clocking (SSC) and residual SSC (Option J11)

External jitter injection

Using an external source connected to delay control input.

User controls

Manual jitter composition

Option J10: PJ 1 / 2, SJ, RJ, sRJ, and BUJ

Option J20: ISI and sinusoidal interference

Option J11: SSC and residual SSC

This screen allows the user to set up combinations of jitter types

and jitter magnitudes easily. Therefore a calibrated ‘stressed

eye’ with more than 50% eye closure can be set up for receiver

testing. Additional jitter can be injected with the interference

channel. It adds ISI and differential/single mode sinusoidal

interference.

Automated jitter tolerance characterization (Option J10)

This test automatically sweeps over SJ frequency based on the

selected start/stop frequency, steps, accuracy, BER level, confi-

dence level and DUT relax time. The green dots indicate where

the receiver tolerated the injected jitter. The red dots show where

the BER level was exceeded. By selecting a tested point, the jitter

setup condition is restored for further analysis. The compliance

curve can be shown on the result screen for immediate result

interpretation. This automated characterization capability saves

significant programming time.

Automated jitter tolerance compliance (Option J12)

This test automatically verifies compliance against a receiver’s jitter

tolerance curve limits specified by a standard or by the user. Most of

the popular serial bus standards define jitter tolerance curves. This

option includes a library of jitter tolerance curves for: SATA, Fibre

Channel, FB-DIMM, 10 GbE/XAUI, CEI 6/11 G, and XFP/XFI. Pass/

fail is shown on a graphical result screen, which can be saved and

printed. A comprehensive compliance report, including the jitter

setup and total jitter results for each test point, can be generated and

saved as a html file for simple jitter tolerance test documentation.

Jitter Tolerance Tests

Figure 3. Manual jitter composition. This allows a combination of jitter types

to be injected. Example shows a typical jitter setup for a PCIe 2.0 add-in

card test

Figure 4. Automated jitter tolerance characterization. The green circles

show where DUT works within the required BER-level

Figure 5. Result screen of the automated jitter tolerance

compliance. A library of jitter tolerance curves is available

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