Agilent Technologies J-BERT N4903B Bedienungsanleitung PDF herunterladen (Seite 5)

J-BERT N4903B The Most Complete Jitter Tolerance Test Solution

Key capabilities of J-BERT N4903B

• Data rate range from 150 to 7 or 12.5 or 14.2 Gb/s

• Calibrated and built-in jitter and interference

sources ( SJ, PJ1, PJ2, SSC, residual SSC, arbitrary

SSC, RJ, BUJ, cm/dm SI, switchable ISI traces) plus

external delay modulation input.

• Supports all clock topologies: embedded clock,

forwarded clock and reference clocked

• Second output channel with independent pattern

+ PRBS

• Excellent signal performance and sensitivity

• Pattern sequencer with 120 blocks, 32Mbit memory

and PRBS

• Electrical idle

• Built-in tunable CDR always included

• Error analysis of 8b/10b and 128b/130b coded and

packetized data. Filtering of definable filler symbols

or PCIe SKPOS

• Extension to data rates up to 28.4Gb/s possible

• Extension with 4-tap de-emphasis possible

• Available as pattern generator version

• Upgrade path from N4903A

Figure 2. J-BERT N4903B The most complete jitter tolerance test

solution for testing embedded and forwarded clock devices

Press Auto Align to automatically adjust

the analyzer’s sampling point delay and

threshold to the center of the eye

Control output voltage of data, aux data,

clock, trigger/ref clock individually

Recover the clock from incoming data with

the built-in CDR with tunable loop bandwidth

Plug-in the interference channel to use the built-

in switchable ISI traces and to inject near-end or

far-end sinusoidal interference

ance tests and fast total jitter measurements.

The J-BERT N4903B is a long-term investment which is configu-

rable for today’s test and budget requirements but also allows

upgrades from the N4903A model, and later retrofit of all options

and full speed when test needs change.

To expand the use of J-BERT a 4-tap de-emphasis, a reference

clock multiplier, a 28 Gb/s 2:1 multiplexer, and a 32 Gb/s CDR

with de-multiplexer can be added to the setup.

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