DP Technology: Main Link Lanes
Silicon structures:
• Structure leveraged from PCI Express
• Implementable on sub 65nm process
• Termination Voltage must be <2volts (internal to IC)
Receiver
• PLL BW=10MHz effective. Jitter tolerance curve specified.
Data Rate
• 1.62 Gbs (RBR)
• 2.7 Gbs (HBR) [units supporting HBR must support RBR]
• 5.4Gbs (HBR2) [units supporting HBR2 must support HBR and
RBR]
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