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Figure 4. Reliable protocol decode with B4621B DDR3 bus decoder

Protocol Analysis

The W3630A series BGA probe

along with the B4621B memory bus

decoder provides complete protocol

decode of memory transactions

using an Agilent logic analyzer as

the analysis execution engine. This

combination provides memory bus

triggering, debug and compliance

verification measurements. Data is

decoded and displayed at any level of

detail from the protocol to binary.The

B4621B protocol-decode software

translates acquired signals into easily

understood bus transactions, at the

full bus speed. The Agilent logic

analyzer provides extensive trigger-

ing and store qualification features.

The DDR protocol-decode software

executes in the logic analyzer and

takes user input on system attributes

such as Burst length, CAS and

Additive Latency, as well as Chip

Selects to decode the key DDR bus

signals and present a display that

lists the transaction type, address,

data and command conditions. The

software also supports user-defined

symbols that can be easily added to

the state listing display.

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Agilent Technologies U4154A Bedienungsanleitung Seite 4