Agilent Technologies N1022A Bedienungsanleitung PDF herunterladen (Seite 4)

Triggering the oscilloscope with a clock

extracted from the probed signal

Sampling oscilloscopes are different from real-time

oscilloscopes in that they require a triggering signal other

than the test signal itself. The triggering signal is often

a clock that is synchronous to the signal under test. In

a probing scenario, a separate system clock for triggering

may not be present. When the necessary synchronous

‘trigger’ is not available, one solution is to derive a clock

from the data being measured. This process is performed

with the 83496A/B clock recovery module.

The N1022A and appropriate probe are connected to

the 83496A/B input port where the signal is evenly split

within the module (see Figure 4). Half is used for clock

extraction; the other half is routed to the 83496A/B front

panel and then connected to the input channel of the

adjacent plug-in module. The 83496A/B will derive a clock

from the data. The recovered clock signal rate is divided

by eight and routed internally in the 86100 mainframe.

The full rate clock or user selected rate divided clock is

available at the 83496A/B front panel and can be useful as

a trigger for eye diagram analysis when data pattern

lengths are multiples of two. (A divided trigger with

an even divisor yields an incomplete eye, see Product

Note 86100-5). Above 7.1 Gb/s, the front panel recovered

clock has a minimum divide ratio of two. The 83496A/B

option 100 requires at least 150 mVpp at its input port

to accurately perform clock extraction. If a 10:1 probe is

used (such as the 1134A), the signal level at the probe

tip must be greater than 1.5 Vpp. If a 3.45:1 probe is used

(such as the 1169A), the signal level at the probe tip must

be greater than 500 mVpp. Note however, that a proper

probe calibration will compensate for both the probe

attenuation and signal splitting within the 83496A/B

and provide an accurate display of signal levels on the

oscilloscope screen. (83496A/B option 101, without

internal splitters, requires half the input signal of

83496A/B option 100 for clock extraction. Any signal

splitting outside the module must be considered when

determining system limits.)

The 83496A/B clock recovery module can derive a clock

from NRZ signals with rates as low as 50 MB/s, as high as

13.5 Gb/s, and any rate between, providing the ultimate

in flexibility and value. (As of 12/06 the data rate must

be entered into the 83496A/B to allow it to properly

synchronize to the signal being probed). As low as

300 femtoseconds rms, the residual jitter of the output

clock is virtually negligible, allowing accurate measurements

of very low levels of signal jitter. The 83496A/B can be

configured with a tunable loop bandwidth. This critical

feature allows the module to be operated as a “golden

PLL” with the optimal loop bandwidth for whatever

standard/data rate is being tested. Loop bandwidth will

control what spectrum of jitter is observed and what is

tracked out from eye-mask and jitter tests. For example,

low frequency jitter can be removed, which is usually of

low importance since system receivers easily tolerate it.

Testing with an optimal loop bandwidth assures that good

parts do not appear to be bad, and bad parts do not

appear to be good. For more information on the use of

clock recovery loop bandwidth, refer to product note

86100-5 “Triggering Wide-bandwidth Sampling

Oscilloscopes for Accurate Displays of High-speed Digital

Communications Waveforms”.

The following configurations for the 83496A/B are available:

Option 100: Electrical differential or single-ended

clock recovery 50 Mb/s to 7.1 Gb/s. The input signal

is internally split and

50% routed back out to the

measurement channel of the adjacent plug-in module.

When measuring differential signals, the most

convenient technique is to use a differential probe

tip, rather than provide two input signals to the

83496A/B. The probe provides a single-ended signal

to the 83496/861XX channel representative of the

difference between the signals at the two probe tips.

The 83496A/B Option 101 electrical/optical clock

recovery module is not recommended for probing

as it does not have an internal signal divider.

It can be used, but requires an external power

divider that precludes the installation of the

N1022A on the front of the clock recovery

module. A complicated adapter scheme is

required. See below.

Special Option 101-H05: This special option

version of the electrical/optical clock recovery

module integrates the signal splitting within the

module. Use for electrical signals is similar to

Option 100. No special adapters other than the

N1022A are required.

Option 200: Increase operating range to 50 Mb/s

to 13.5 Gb/s. Available for either Option 100

or Option 101 configurations. When measuring

clocks, rates from 25 MHz to 7.75 GHz are allowed.

Option 300: Add golden PLL (tunable loop bandwidth

capability). Loop bandwidth is tunable from 30 KHz

to over 10 MHz. (Without Option 300, the loop

bandwidth can be configured at two discrete settings,

dependent upon data rate).

Option 200 and 300 can also be added at a later date.

The module must be returned to an Agilent service center

for the upgrade.

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