Agilent Technologies InfiniiVision 7000B Series Bedienungsanleitung PDF herunterladen (Seite 6)

6

A quick tour of the application (continued)

Triggering on valid states

MSOs incorporate logic state triggering

for triggering on specific states. Set

up a valid state trigger by specifying

the appropriate LAI clock edge and the

desired bus/signal pattern. Because

the LAI core outputs both the clock

signal and bus values, triggering on the

combination ensures your state trigger

is valid—even though the digital

channels are sampling asynchronously.

Track valid states by measuring the

bus value on each falling clock edge

for the image shown.

Correlate internal FPGA activity with

external measurements

View internal FPGA activity and time-

correlate internal FPGA measurements

with external analog and digital events

in the surrounding system. FPGA

Dynamic Probe unlocks the power of

the MSO for system-level debug with

FPGAs.

Setup complete: Make measurements

Quickly change which signal bank is

routed to the MSO. A single mouse

click tells the LAI core to switch

to the newly specified signal bank

without any impact to the timing of

your design. To make measurements

throughout your FPGA, change signal

banks as often as needed. With each

new selection of a signal bank, FPGA

Dynamic Probe updates new signal

names from your design to the MSO.

User-definable signal bank names

make it straight forward to select a

part of your design to measure.

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