FuturePlus Systems Corporation DDR2 DIMM HIGH SPEED PROBE FS2334 Users Manual For use with Agilent Technologies
10FS2334 Frontside layout FS2334 Backside layout Test Points There are several test point on the board. The first set of test points are used to se
11 DM2_DQS11 is not brought to the logic analyzer, but it can be probed at TP4 DQS5n is not brought to the logic analyzer, but it can be probed at TP
12Recommended Logic Analyzer Card Requirements and Configuration files 169xx Analyzer Type Timing Analysis State Analysis 667MT/s or slower 16753/4
13 Logic Analyzer card configurations – Note: These are all for unbuffered DIMM probing FS234_1 2 machine, 7 Card 800MT/s Read and Write configurat
14 Software Requirements Setting up the 169xx Analyzer A CD containing the 16900 software is included in the FS1136 package. The CD contains a setup
15 Offline Analysis Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to us
16 After the decoder has loaded, select Preferences from the overview screen and set the preferences to their correct value in order to decode the tr
17 TimingZoom Analysis The TimingZoom feature of the 1690x logic analyzer allows for efficient timing analysis of all the signals on the DDR2 DIMM bu
18 State Analysis Overview There are several choices for State mode analysis using the FS2334 DDR2 probe depending on the speed of the data bus being
19 State Analysis Operation – Read and Write at 667MT/s or slower State mode capture is performed by using both edges of CK0. This double probing o
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20 The process for setting sampling positions at speeds of 800MT/s: This procedure requires the probe user to capture TimingZoom traces and use the
21 State analysis calibration procedure This process is in large part the same for both use in the 7 card Read and Write configuration at 800MT/s an
22 4) Repeat this procedure using the next rising edge of Write – Command:CK2_TZ and the corresponding data burst cycle (it will be right next to th
23label to be set to the same value. Then you can drag the blue sample position bar back to the right to place it in the position you measured in st
24 Adjusting the sampling positions with controlled stimulus This is a special case requiring special stimulus of the DDR2 DIMM bus. This may involve
25signal edges change relative to the Data Strobes (clock input) and this will be close the valid eye openings for all the Data signals. Run Auto Sam
26 State Display The following figure shows a typical DDR2 screen display. Because the analyzer may sample data on both edges of the clock (FS1117)
27 DDR2 Protocol Checking and Performance Tool (FS1140) The FS1140 DDR2 Protocol Checking and Performance Tool is a separate VBA-based application th
28 Setting up the FS1140 DDR2 Tool The FS1140 DDR2 tool has to be set-up with the DDR2 bus parameters being used on the target system in order to i
29 Functional and Performance Analysis – NOTE: The Functional Performance portion of this software will NOT work with 2 FRAME configurations This wi
3Overview... 18
30Export This function takes the data captured and exports it in .csv format to a location the user selects. Repetitive Run This function allows the
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32 Appendix FS2334 Signal to Logic Analyzer Connector and Channel Mapping The following table shows how the FS2334 DDR2 Probe connects DDR2 DIMM sign
33Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 4
34Header 2 - Command Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name
35Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 NC
36Header 3 - Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Gr
37Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ
38Header 4 - Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Gr
39Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ
4 How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-273
40Header 5 - Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Gr
41Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 CB
42 Header 14 – ECC bits only this header is not in any config file Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer c
43Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 5
44Header 6 – Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name G
45Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 5
46 Header 7 -Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Gr
47Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 5
48 Header 8 - Write Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name G
49Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 5
5 Product Warranty Due to wide variety of possible customer target implementations, the FS2334 DDR2 DIMM probe has a 30 day acceptance period by the
50Header 12 – Read – Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number S
51Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ
52Header 10 - Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Si
53Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ
54Header 11 – Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Sig
55Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 CB
56Header 9 – Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Sig
57Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ
58Header 13 – Read Duplicates - only data signals Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Si
59Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ
6 Software License Agreement IMPORTANT - Please read this license agreement carefully before opening the media envelope. Rights in the software are
7 Introduction Thank you for purchasing the FuturePlus Systems FS2334 DDR2 DIMM Interposer Logic Analyzer Probe. We think you will find the FS2334, a
8 FS2334 Probe Description The FS2334 DDR2 Probe allows you to perform timing analysis measurements on DDR2 DIMM busses. It also provides a Protocol
9 Signal Assignments on Probe Pods The overlap in the bit ranges (for DQxx) signals between pods occurs because the bits are assigned to pods in the
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