Agilent Technologies 16700 SERIES LOGIC ANALYSIS SYSTEM 16700 Bedienungsanleitung PDF herunterladen (Seite 4)

The next step for the example is set-

ting up the trigger condition. We are

going to trigger on a count of ‘0’ to

demonstrate the cross-triggering

capabilities of a 16700 Series logic

analysis system and an ILA. Notice

that the trigger action includes "arm

out" along with trigger and fill memo-

ry. The arm out action only appears

when the output port from the ana-

lyzer is used. Don’t start the acquisi-

tion yet. We still need to set up the

ILA through the ChipScope interface.

Figure 6. Triggering on count of ‘0’ with "arm out" active

Setting up the Xilinx ILA

We can directly probe internal signals

with the ILA. In this example, the

lower 32 bits of the ILA are probing

the counter registers. The 33rd bit is

probing the 15th bit of the control

bus. This signal is the internal repre-

sentation of the trigger out from the

ILA. A segment from the Verilog

source code for the example circuit is

listed below in Figure 7.

module top_apps (clk,led,count);

input clk;

output led;

output [31:0] count;

wire [41:0] control_bus0;

wire [31:0] count;

demo counter (

.clk(clk),

.led(led),

.count(count));

ila_dd1024_dw33_tw32_e2 U0_ila_dd1024_dw33_tw32_e2 (

.CONTROL(control_bus0),

.CLK(clk),

.DATA({control_bus0[14],count}),

.TRIG(count));

icon U_icon (

.CONTROL0(control_bus0));

endmodule

Figure 7. Sample of Verilog source code for the example circuit

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