Available N4903A configurations:
Speed classes, including built-in CDR:
150 Mb/s to 12.5 Gb/s N4903A-C13
150 Mb/s to 7 Gb/s N4903A-C07
Jitter Tolerance Options:
RJ, PJ, SJ, BUJ injection N4903A-J10
ISI and Sinusoidal N4903A-J20
Interference injection
Compliance suite N4903A-J12
Upgrade to RJ, SJ, PJ, BUJ N4903A-U10
Upgrade to Compliance Suite N 4903A-U12
Upgrade to 12.5 Gb/s N4903A-U13
Upgrade to ISI and S.I. N4903A-J20
Pattern Generator Options:
SSC clocking N4903A-J11
(only in combination with–J10)
Error Detector Options:
Bit Recovery Mode N4903A-A01
Upgrade to CDR N4903A-UTR
with tunable loop bandwidth
J-BERT N4903A High-Performance Serial BERT Data Sheet 3
J-BERT key characteristics:
• 150 Mb/s to 7 Gb/s or 12.5 Gb/s – enough margin for
characterizing today’s most popular serial interfaces
• Calibrated and integrated jitter injection (opt. J10). All
in one box: RJ, PJ, BUJ, ISI, sinusoidal interference to
stress the receiver with >50% eye closure
• Automated and compliant jitter tolerance tests covers
popular serial bus standards: PCI Express, SATA, Fibre
Channel, SATA, FB-DIMM, CEI 6G/11G, 10GbE/XAUI,
XFI/XFP
• Delay control input for generator to apply any external
jitter source
• Bit recovery mode to test unknown data traffic
• Pattern sequencer to generate complex training
sequences
• SSC clocking for computer buses
• Subrate clocks to generate reference clocks easily
• Differential I/O for DATA and CLOCK and most
supplementary signals for testing serial interfaces
• Integrated CDR (clock data recovery) to test clock-
less interfaces
• Upgrade option for tunable loop bandwidth CDR
• Highest performance BERT for accurate measurements
• All options retrofitable
J-BERT N4903A High-Performance
Serial BERT
The J-BERT N4903A High-Performance Serial BERT
provides the only complete jitter tolerance test.
It is the ideal choice for R&D and validation teams
characterizing and stressing chips and transceiver
modules that have serial I/O ports up to 7 Gb/s or
12.5 Gb/s. It can characterize a receiver’s jitter tol-
erance and prove its compliance to today’s most
popular standards, such as PCI Express, SATA,
Fibre Channel, Fully Buffered DIMM, CEI, 10 GbE/
XAUI, and XFP/XFI.
Accurate characterization is achieved with clean sig-
nals from the pattern generator, which feature excep-
tionally low jitter and extremely fast transition times.
Test set-up time is reduced significantly, because
the J-BERT N4903A matches most recent serial bus
standards optimally:
• undeterministic patterns can now be analyzed
with the Bit Recovery Mode.
•A pattern sequencer helps to set up training
sequences quickly, to get complex devices into
loop-back test mode.
• Reference clocks can be provided by the subrate
clock outputs, which can generate any ratio of
clock to data rate.
• All I/Os are differential and a built-in CDR allows
testing of clock-less interfaces.
The J-BERT N4903A is a future-proof Serial BERT
platform, which is configurable for today’s test and
budget requirements but also allows upgrades to all
options and full speed.
Measurements
BER and Measurement suite
• BERT Scan
• Output Timing Jitter
• Spectral Jitter Decomposition
• Eye Contour
• Quick Eye diagram and BER contour
• Fast Eye Mask
• Output Level and Q Factor
• Error Location Capture
• Fast Total Jitter
• Pattern capture
Jitter Tolerance Tests:
• Manual Jitter Composition (opt. J10)
• Automated Jitter Tolerance
• Characterization (opt. J10)
• Automated Jitter Tolerance Compliance (opt. J12)
Applications
• PCI Express
•SATA
• Fibre Channel
• Fully Buffered DIMM
• CEI
• 10 GbE /XAUI
• XFP/XFI
(20 Seiten)
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