
9
Serial BERT N4906B, Data Sheet V.3
Figure 16: Output blanking
Auxiliary Input
When the alternate pattern mode is activated the
memory will be split into two parts. The user can
define a pattern for each part. Depending on the
operational mode of the auxiliary input the user
can switch in real-time the active pattern by apply-
ing a pulse (mode 1), or by a logical state (mode 2),
to the auxiliary input.
If the alternate pattern mode is not activated the
user can suppress the data on the data output by
applying a logical high to the auxiliary input (mode
3).
Mode 1: one-shot edge sensitive alternating
pattern
A rising edge on the auxiliary input inserts a
single version of pattern B into repetitions of
pattern A. The applied pulse must be 512 bit long.
Mode 2: level sensitive alternate pattern
(continuous)
The logic state of the signal at the auxiliary
input determines which pattern is output. An
active (TTL high) signal will output pattern B.
Mode 3: output blanking
If alternate pattern mode is not selected, an active
(TTL high) signal at the auxiliary input port forces
(gates) the data to a logic zero at the next 32-bit
boundary in the pattern. The minimum length of
the signal is 100 ns.
Figure 14: Edge sensitive
Figure 15: Level sensitive
Table 6: specifications for auxiliary input
Interface DC coupled, 50 Ω nominal
Levels TTL compatible
Connector SMA female
External error inject input
The external “error inject input” adds a single
error to the data output for each rising edge at the
input.
Table 7: Specifications for error inject input
Interface DC coupled, 50 Ω nominal
Levels TTL compatible
Connector SMA female
9
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