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Auxiliary output (AUX OUT)

This output can be used to provide either clock or data signals:

Clock: clock signals from the input or the recovered clock signals

in CDR mode.

Data: weighted and sampled data.

Table 26. Speciﬁ cations for the auxiliary output

Amplitude 600 mV typical

Interface AC coupled, 50 Ω nominal

Connector SMA female

Gating input (GATE IN)

If a logical high is applied to the gating input the analyzer will

ignore the incoming bits during a BER measurement. The ignored

bit sequence is a multiple of 512 bits. For measuring data in

bursts of bits, rather than a continuous stream of bits, a special

operating mode is used. This is the burst sync mode. In this case,

the signal at the gating input controls the synchronization and the

error counting for each burst.

This is an important feature for recirculation loop measurements.

If clock data recovery (CDR) is used to recover the clock from the

burst data, the CDR takes 2 µs from the start of the burst data

to settle. The number of bits needed to synchronize itself during

a burst depends on whether the pattern consists of hardware

based PRBS data or memory based data. To run properly in burst

mode the system needs a backlash of data after the gating input

returns to high. During each burst, the gating input has to remain

passive.

Error Detector Speciﬁ cations

Table 27. Speciﬁ cations for gating input

Burst synchronization time 1536 bits for PRBS

15 kbit for pattern

Backlash 1536 bits in non-CDR mode

1.5 µs in CDR-mode

Gate passive time

2560 bits in non-CDR mode

2560 bits or 1.5 µs whichever

is longer, in CDR mode

Interface levels TTL levels

Pulse width 256 clock periods

Connector SMA female

Pattern capture

The error detector can capture up to 32 MB data bits from the

device under test. The captured data bits are displayed in the

pattern editor in hex or binary format. The data bits can be

used as expected data for BER testing or can be saved for post

processing.

Figure 28. Burst mode allows recirculation loop testing

Checked data

Backlash

CDR

settling

time

Sync. time

Burst

High

Low

Gate input

Data input

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