Agilent Technologies N5980A Bedienungsanleitung PDF herunterladen (Seite 8)

Table 7: Specifications for subrate clock output

Divider factors n = 2,3…128

Levels High: + 0.5 V

Low: --0.5 V typical

Transition times 35 ps typical

Interface DC coupled, 50 W, differential

or single-ended

Connector SMA female

Table 8: Specifications for the 10 MHz reference output

Amplitude 1V into 50 W typical

Interface AC coupled,

50 W output impedance

Connector BNC, rear panel

8 J-BERT N4903A High-Performance Serial BERT Data Sheet

Clock output (CLK OUT)

Table 3: Clock output characteristics. All timing parameters

are measured at ECL levels.

Frequency range 150 MHz to 12.5 GHz (opt. C13)

Can be programmed up to

13.5 GHz

150 MHz to 7 GHz (opt. C07)

<620 MHz only with external

clock

Amplitude/resolution 0.1 V pp to 1.8 V pp, 5 mV steps

Output voltage window --2.00 to +2.8 V

Transition times

(20% to 80%) < 20 ps

(10% to 90%)

< 25 ps

External termination --2 V to +3 V

voltage

Jitter 1 ps rms typical with disabled

jitter sources and internal clock

SSB phase noise < --75 dBc with internal

clock source, 10 GHz @ 10

kHz offset, 1 Hz bandwidth

Interface

Differential or single-ended,

DC coupled, 50 W output

impedance

Connector 2.4 mm female

At 10 Gb/s and 7 Gb/s

For positive termination voltage or termination to GND, external

termination voltage must be less than 3 V below VOH. For

negative termination voltage, external termination voltage

must be less than 2 V below VOH. External termination volt

age must be less than 3 V above VOL.

Unused outputs must be terminated with 50 W to GND.

Table 4: Specifications for clock input and 10 MHz reference

input

Amplitude 200 mV to 2 V

Interface AC coupled, 50 W nominal

Connectors

- Clock input: SMA female, front panel

- 10 MHz reference input: BNC, rear panel

Clock Input (CLK IN)

There are two modes when using the clock input con-

nector.

External Clock mode: all output signals of the gener-

ator follow the external clock and its modulation.

Nevertheless, the modulation of the external clock

must be within the same range given for SSC and SJ

(see tables 11 and 21) or the 500 ps delay line. When

using External Clock mode the internal SSC and SJ

sources and the 500 ps delay line for PJ injection are

disabled. Modulation using the

200 ps delay line is still available (see figure 24).

External PLL mode: it is used to lock the generator

to an external clock at the same data rate. The pro-

vided clock must not be modulated in external PLL

mode. All internal jitter sources are available.

Delay control input (DELAY CTRL IN)

The external signal applied to delay control input, varies

the delay between data output and clock output. This can

be used to generate jittered signals to stress the device

under test in addition to the calibrated jitter injection

from N4903A.

Error add input (ERROR ADD)

The external error add input adds a single error to the

data output for each rising edge at the input.

Subrate clock output (SUB CLK OUT)

The subrate clock output is used to generate

reference clocks, which are subrates of the data rate, for

example, a 100 MHz clock for 2.5 or

5 Gb/s PCI Express data rate.

10 MHz reference input (10 MHz REF IN)

It is used to lock the generator to an external 10 MHz

reference clock. The data rate can be selected within

the same range as if the internal clock would be used.

The provided reference clock must not be modulated.

All internal jitter sources are available.

Specifications-Pattern Generator

Table 5: Specifications for delay control input

Range --100 ps to +100 ps

Sensitivity 400 ps/V typical

Linearity ± 5 % typical

Modulation 1 GHz typical at 10.8 Gb/s

bandwidth data rate

Levels --250 mV to +250 mV

Interface DC coupled, 50 W nominal

Connector SMA female

10 MHz Reference output (10 MHZ REF OUT)

VCO

External Clock (Ext. PLL mode)

Internal Clock

10 MHz Ref Clock

External Clock

PLL

Clock generator

Figure 14: N4903A clock modes

Table 6: Specifications for error inject input

Levels TTL compatible

Interface DC coupled, 50 W nominal

Connector SMA female

External CLock

10 MHz Ref Clock

Clock Generator

Internal Clock

External Clock

(Ext. PLL mode)

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 17 18

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