Agilent Technologies 16800 Series Bedienungsanleitung PDF herunterladen (Seite 2)

FPGA dynamic probe lets you:

View internal activity – With a

logic analyzer, you are normally

limited to measuring signals at

the periphery of the FPGA. With

the FPGA dynamic probe, you can

now access signals internal to the

FPGA. You can measure up to 256

internal signals for each external

pin dedicated to debug, unlocking

visibility into your design that

you never had before.

Make multiple measurements in

seconds – Moving probe points

internal to an FPGA used to be

time consuming. Now, in less than

a second, you can easily measure

different sets of internal signals

without design changes. FPGA

timing stays constant when you

select new sets of internal signals

for probing.

Leverage the work you did in your

design environment – The FPGA

dynamic probe maps internal

signal names from your FPGA

design tool to your Agilent logic

analyzer. Eliminate unintentional

mistakes and save hours of time

with this automatic setup of

signal and bus names on your

logic analyzer.

Board

JTAG

Altera programming hardware

Parallel

or USB

FPGA

Probe outputs

on FPGA pins

SW application supported

by 1680, 1690, 16800 and

16900 Series logic analyzers

LAI

Figure 2. The FPGA dynamic probe requires Altera’s Quartus II design software with

its logic analyzer interface and Altera programming hardware setup. The Quartus II

(ver. 6.0 or higher) logic analyzer interface allows you to create and insert the core for

use by the FPGA dynamic probe application on the logic analyzer. This configuration

allows you to probe the FPGA pins with the Agilent FPGA dynamic probe software. The

FPGA dynamic probe controls which group of internal signals to measure via the

Altera programming hardware connected to the JTAG port of the FPGA.

To FPGA pins

Selection MUX

1-256

Select

1-256

JTAG

1-256

Change signal bank

selection via JTAG

Figure 3: Access up to 256 internal signals for each debug pin. Signal

banks all have identical width (1 to 256 signals wide) determined by

the number of device pins you devote for debug. Each pin provides

sequential access to one signal from every input bank.

Debug your FPGAs faster and more effectively with a logic analyzer

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